Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture

This paper describes the implementation of the Advanced Encryption Standard (AES) for a specific hardware architecture, which was developed based on the combination of different design paradigms. The architecture comprises synchronous and systematic bit–serial processing without a central controlling instance. To realize the AES cipher, we extended the architecture by designing specific elements. That means, we deeply analyzed the encryption algorithm and identified hardware characteristics leading to an optimal area and run–time efficient implementation. The implementation of AES is done with the developed synthesis tool of the hardware architecture in synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran some tests on an FPGA board.